As scaling for conventional CMOS integrated circuits approaches quantum mechanical limits, alternative nanostructures and materials have been investigated in the semiconductor industry. Of such nanostructures and materials, carbon nanotubes (CNTs) offer excellent intrinsic properties that are suitable for high performance nanoscale devices.
A key advantage of CNTs over conventional CMOS devices is that scaling limitations of MOSFETs due to boundary scattering of electrons from imperfect interfaces are solved naturally in CNTs which have a smooth, well coordinated graphene structure with no bonds to the outside. This enables CNTs to retain excellent transport properties to much smaller lateral dimensions than silicon. The small radius and possibility of completely surrounding the CNT by a gate provide excellent electrostatic confinement of channel electrons, enabling the channel length to be scaled down to very small dimensions, and their small size would enable high packing densities. Band structure calculations of CNTs according to P. Avouris and J. Chen, “Nanotube electronics and optoelectronics,” Materials Today, Vol. 9, pp. 46-54, (2006) show that conduction and valence bands are mirror images of each other, i.e., both electrons and holes should share equally good transport properties. This indicates suitability of CNTs for a general-purpose high-performance complementary circuit technology.
As is now well known, CNTs can be either metallic or semimetallic, depending on their chirality and have a bandgap which is inversely proportional to their diameter for the semiconducting tubes. A useful relation, derived from tight binding calculations, between the diameter and the band gap, Eg of a CNT isEg=γ(2dC—C/√{square root over (3)}dCNT),  equation (1)where γ is the hopping matrix element, dC—C is the C—C bond distance, and dCNT is the diameter of the carbon nanotube. Inclusion of electron-electron interactions raises the size of the bandgap, Eg significantly. For a 1 nm nanotube, the band gap is roughly 1 eV. The best transport measurements and device characteristics have been obtained on rather larger diameter nanotubes, with their diameter in the 1.7-3 nm range. The idealized electron/hole dispersion relation is hyperbolic in shape, with a quasi parabolic “effective mass” regime at lower energies and a linear “constant velocity” regime at higher energies, where the limiting velocity, vlim, is ˜5−10×107 cm/sec according to G. Pennington and N. Goldsman, “Semiclassical transport and phonon scattering of electrons in semiconducting carbon nanotubes,” Phys. Rev. B 68, 045426 (2003).
Methods of inducing one type of charge carriers, e.g., holes or electrons, in a carbon nanotube are known in the art. Typically, a hole-inducing material layer or an electron-inducing material layer may be deposited on a carbon nanotube to induce either holes or electrons within the carbon nanotube. For example, methods disclosed in J. Chen, et al., “Self Aligned Carbon Nanotube Transistors with Novel Chemical Doping,” 2004 Transactions of the International Electron Device Meeting, pp. 695-698, (2004) and D. Kang et al, “Oxygen-induced p-type doping of a long individual single-walled carbon nanotube” Nanotechnology 16 pp. 1048-1052, (2005) may be employed to form a carbon nanotube of one conductivity type, i.e., a carbon nanotube in which one type of charge carriers are predominant over the opposite type of charge carriers. Contacts and electrodes may be formed on such a carbon nanotube to form a discrete semiconductor component such as a discrete transistor.
Fabrication of an integrated circuit comprising multiple discrete carbon nanotube devices and an interconnect wiring that provides electrical connections amongst them is a more difficult challenge than formation of a carbon nanotube based discrete semiconductor component. This is because carbon nanotubes are formed as discrete wires that need to be aligned on a substrate. While technological advances are being made to improve alignment of carbon nanotubes, alignment of carbon nanotubes still requires meticulous manipulation of discrete carbon nanotubes.
The lack of ability to tailor the size of carbon nanotubes and to place them in arbitrary location and orientation is a major constraint in fabricating an integrated carbon nanotube circuit. The difficulty of fabricating an integrated circuit out of carbon nanotubes due to this constraint is readily seen when typical semiconductor structures are examined. As an illustrative example, a prior art static random access memory (SRAM) cell formed by conventional semiconductor manufacturing methods is employed herein. SRAM is a memory device employing six transistors. SRAM cell design typically begins by picking the smallest PFET supported by a given technology for two pull-up PFETs, followed by scaling of NFET pass gate transistors and pull-down NFET transistors for optimal beta ratio, cell stability, and access time.
Referring to FIG. 1A-1C, an exemplary prior art SRAM structure comprises a first pull-up PFET 16, a second pull-up PFET 16′, two pull down NFETs (14, 14′), and two pass gate NFETs (12, 12′). FIG. 1A is a top-down view of the exemplary prior art structure up to the CA level not showing a middle-of-line (MOL) dielectric 70. FIG. 1B is a vertical cross-sectional view of the exemplary prior structure along the plane B-B′ showing the MOL dielectric 70. FIG. 1C is a vertical cross-sectional view of the exemplary prior structure along the plane C-C′ showing the MOL dielectric 70. Each of the transistors (12, 12′, 14, 14′, 16, 16′) comprise a portion of the semiconductor substrate 10, a gate dielectric 30, a gate conductor 32, a gate spacer 34, active area (AA) silicides 60, and gate top silicides 64. Shallow trench isolation 20 physically separates the transistors (12, 12′, 14, 14′, 16, 16′) and provides electrical isolation among the transistors (12, 12′, 14, 14′, 16, 16′). CA contact vias 76 and CA bars 78 are employed to provide electrical wiring among the transistors (12, 12′, 14, 14′, 16, 16′). One of the CA bars 78, which contacts one of the AA silicides 60 of the first pull-up PFET 16 as well as the gate top silicides 64 of the second pull-up PFET 16′ as shown in FIG. 1B, provides electrical connection between the drain of the first pull-up PFET 16 and the gate of the second pull-up PFET 16′. Likewise, another CA bar 78 provides electrical connection between the drain of the second pull-up PFET 16′ and the gate of the first pull-up PFET 16.
Referring to FIGS. 2A-2C, the exemplary prior art SRAM structure is shown up to the M1 level. FIG. 2A is a top-down view of the exemplary prior art structure up to the M1 level not showing the middle-of-line (MOL) dielectric 70 and an M1 dielectric 80. FIG. 2B is a vertical cross-sectional view of the exemplary prior structure along the plane B-B′ showing the MOL dielectric 70 and the M1 dielectric 80. FIG. 2C is a vertical cross-sectional view of the exemplary prior structure along the plane C-C′ showing the MOL dielectric 70 and the M1 dielectric 80. M1 wires 88 embedded within the M1 dielectric 80 contact the underlying CA contact vias 76 and the CA bars 78. In the exemplary prior art SRAM structure, FIGS. 2A and 2C illustrate that the drain of each of the two pull-up transistors (16, 16′) is electrically connected to a node at which a source/drain of one of the pass gate transistors (12, 12′) adjoins the drain of one of the pull-down NFETs (14, 14′) by a combination of a CA bar 78, an M1 wire 88, and a CA contact via 76. Two such combinations are present in each SRAM cell structure which comprises six transistors (12, 12′, 14, 14′, 16, 16′).
Referring to FIG. 3, a circuit schematic 18 for the exemplary prior art SRAM structure shows a first pair of a first pass gate n-type field effect transistor (NFET) 2 and a first pull-down n-type field effect transistor (NFET) 4 wherein a first source/drain of the first pass gate NFET 2 and a first drain of the first pull down NFET 4 are adjoined to form an electrical connection. In the physical structure, this electrical connection is achieved by a first common active area that contains both the first source/drain of the first pass gate NFET 2 and the first drain of the first pull-down NFET 4. Similarly, a second source/drain of the second pass gate NFET 2′ and a second drain of a second pull-down NFET 4′ are adjoined to form another electrical connection. In the physical structure, this electrical connection is achieved by a second common active area that contains both the second source/drain of the second pass gate NFET 2′ and the second drain of the second pull-down NFET 4′. The circuit schematic 18 further comprises a first pull-up p-type field effect transistor (PFET) 6 containing a third drain, which is physically a third active area, and a second pull-up PFET 6′ containing a fourth drain, which is physically a fourth active area. Each of the source/drain nodes of the pass gate transistors (2, 2′) may function as a source or a drain depending on the operation of the SRAM circuit.
The third active area is electrically connected to the first active area via a collection of a first contact via, a first M1 wire, and a first CA bar. This connection is represented in the circuit schematic 18 by a first internal node 11. Similarly, the fourth active area is electrically connected to the second active area via a collection of a second contact via, a second M1 wire, and a second CA bar. This connection is represented in the circuit schematic 18 by a second internal node 11′. The gates of the second pull-up PFET 6′ and the second pull-down NFET 4′ are adjoined to the third drain of the first pull-up PFET 6 via the first CA bar. This connection is represented in the circuit schematic 18 by a third internal node 13A and a fourth internal node 13B. The gates of the first pull-up PFET 6 and the first pull-down NFET 4 are adjoined to the fourth drain of the second pull-up PFET 6′ via the first CA bar. This connection is represented in the circuit schematic 18 by a fifth internal node 13A′ and a sixth internal node 13B′. The internal nodes (11, 11′, 13A, 13B, 13A′ 13B′) are connected by CA contact vias 76 and CA bars 78 as well as M1 wires 88. Bit line wiring (15, 15′) and word line wiring (17, 17′) are typically implemented at M2 and M3 levels.
One important aspect of the exemplary prior art SRAM structure is the ability to form two dimensional active areas in any size, in any location, and, unless limited by design rules, in any orientation. Since the relative location of the components of the exemplary prior art SRAM is fixed in a top-down view, the interconnect wiring may be formed by aligning interconnect level masks to the pattern of the components in a lower level. Thus, the layout of circuit components in the exemplary prior art SRAM is inherently two dimensional, which is reflected in the circuit schematic in FIG. 3. In general, conventional silicon based semiconductor devices are formed taking full advantage of a two-dimensional layout to reduce the number of wiring levels, and consequently, to reduce cost.
FIG. 4 is a schematic of an exemplary prior art latch circuit which takes in an input signal from a data node labeled “data” at a specific phase of a signal on the clock node labeled “c2,” for example, at a positive transition or at a negative transition, and stores data on the latch L2 and provides an output to the output node labeled “L2_n.” The circuit layout is two dimensional, and so are typical physical implementations of this circuit layout in a semiconductor device.
As discussed above, however, the carbon nanotubes do not easily render themselves to positioning in arbitrary locations or angles on a substrate. An ordered arrangement of carbon nanotubes is a low entropy state, and manufacture of such a highly ordered arrangement of carbon nanotubes is consequently prone to low yield. For a carbon nanotube based integrated circuit to have realistic and economical manufacturability, requirement on the physical arrangement of the carbon nanotubes needs to be minimal. Thus, simple arrangements of a carbon nanotube, or even fabrication of an integrated circuit on a single carbon nanotube would be desired.
In view of the above, there exists a need for a carbon nanotube based semiconductor circuit structure that is technologically less demanding, easily manufacturable, and economical.
Particularly, there exists a need for a carbon nanotube based semiconductor circuit structure in which as many circuit elements are manufactured on the same nanotube to minimize alignment requirement on the carbon nanotubes.
Further, there exists a need for a carbon nanotube based semiconductor circuit structure in which the pattern of arrangement of the carbon nanotubes is as simplified as possible, as well as simplifying the pattern of the materials needed to render the carbon nanotubes functional, such as hole-inducing material layers and electron-inducing material layers.